Verification Techniques for System-Level Design
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About the Book
Verification Techniques for System-Level Design
Book Details
ISBN-13: 9780123706164
EAN: 9780123706164
Publisher Date: 01 Nov 2007
Binding: Hardback
Continuations: English
Dewey: 621.381
Height: 235 mm
Illustrations: Approx. 130 illustrations
LCCN: 2007028038
No of Pages: 256
Pagination: 256 pages, Approx. 130 illustrations
Series Title: Systems on Silicon
Star Rating: 2
Year Of Publication: 2007
ISBN-10: 0123706165
Publisher: Elsevier Science & Technology
Acedemic Level: English
Book Type: English
Depth: 25
Gardner Classification Code: K00
Illustration: Y
Language: English
MediaMail: Y
Number of Items: 01
PrintOnDemand: N
Spine Width: 22 mm
Width: 191 mm
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